1. Field of the Invention
This invention relates to a semiconductor memory device and an electric device with the same.
2. Description of Related Art
Currently known EEPROMs are usually formed of memory cells with floating gates in which charges are stored in a non-volatile manner. Arranging NAND cell units each having a plurality of memory cells in series, a cell array of a NAND type flash memory, which is known as one of these EEPROMs, is configured. Source and drain diffusion layers are shared with adjacent memory cells in the NAND cell unit. Therefore, the NAND flash memory has a feature that it is possible to achieve a large capacity with a relatively small chip size by increasing number of memory cells in the NAND cell unit.
As described above, in the NAND type flash memory, a NAND cell unit is formed of serially connecting plural memory cells, and connected to a bit line via a select gate transistor. Data read operation is performed by detecting whether the bit line is discharged or not by a selected cell, or whether the bit line discharge is large or not. To non-selected cells, a pass voltage is applied, which makes the cells on in spite of the cell data. However, due to the fact that plural memory cells are serially connected in the NAND cell unit, the channel resistance of the NAND cell unit is large, thereby resulting in that read out cell current is small.
For this reason, it takes a long time until the bit line voltage difference becomes to be a predetermined value due to cell data. Usually, it is required of taking a data read time of 20 to 25 μsec. The memory chip outputs a busy signal during the data read operation, which notes that the chip is in a data read operation state.
FIG. 13 shows a data read operation of a conventional NAND type flash memory. Input write enable signal WEn(=“L”) and address enable signal ALE(=“H”) from the chip external, and input address from I/O terminal, and data read operation for cell array starts. Usually, in the NAND type flash memory, data read is done by one page. When data read starts, busy signal R/B=“L” (True Busy) is output to the external of the chip.
After the read operation has been performed for a predetermined time, 1 page read out data held in the sense amplifiers is output to the I/O terminal via an I/O buffer in response to read enable signal REn. Up to this, one cycle of data read is done. That is, one cycle of the data read operation includes a data read operation from the cell array to the sense amplifier (hereinafter refers to “cell data read” operation) and an output operation for outputting the data held in the sense amplifier to the chip external (hereinafter refers to “read data output” operation). In order to sequentially read out plural pages, similar read cycles are periodically performed.
FIG. 14 shows another data read operation, a data read time of which is shortened by use of address increment. In this case, address input operations are omitted for the following pages. Once the head address is input in the first cycle, internal addresses are incremented in the following cycles, whereby sequential read operations may be done.
In both cases of FIGS. 13 and 14, while the busy signal, R/B=“L”, is output, it is impossible to do a cell data read operation. If the number of cells in a NAND cell unit is more increased, and the memory capacitance becomes larger, the cell current becomes smaller, whereby it takes a longer time for a data read operation.
By adding a data circuit (for example, shift register) for temporally hold the read out data from the cell array, read/write operation speed may be improved (for example, Japanese Patent Application Laid Open No. 2002-15585).
To increase the capacitance without changing the specification of the NAND type flash memory, plural cell array blocks with the same capacitance are arranged. In this case, the respective cell array blocks have row decoders and sense amplifiers in order to make them independently accessible of each other.
In such a large capacitive NAND type flash memory, and in such a case that data of the plural cell blocks are sequentially read, if it is necessary to use a method that an address input is done for each read operation, and a busy signal is output during each cell data read operation, high-speed data read becomes to be difficult. For example, in a case that various status data (defect address dada, protect information, history information, ID information and the like) stored in all cell blocks are read out to be checked at a power-on time of the memory chip, it takes a very long time in spite of that the data amount is little.